1. Field
Example embodiments of the present invention relate to a semiconductor memory device, and in particular, to a read data path circuit for use in a semiconductor integrated circuit device such as a dynamic random access memory.
2. Description of the Related Art
There is a movement towards developing semiconductor memory devices including dynamic random access memories (hereinafter, referred to as DRAMs) with a high degree of integration and high speed. DRAMs have memory cells and are generally adopted as main memories for electronic systems. Each of the memory cells includes one access transistor and one storage capacitor
Referring to FIG. 1, in a general data processing system, a DRAM 10 adopted as a main memory is connected to a micro processing unit 2 through a system bus B1. The micro processing unit 2 is connected to a flash memory 4 through a system bus B5, performs a processing operation set in accordance with a program stored in the flash memory 4, and controls a drive unit 6 through a control bus B2 as occasion demands. In order to perform a processing operation for controlling the drive unit 6, the micro processing unit 2 performs a data accessing operation to write data in memory cells of the DRAM 10 and read data from memory cells.
During a read operation, data stored in memory cells of the DRAM 10 are transmitted to pairs of bit lines and are sensed and amplified by bit line sense amplifiers (hereinafter, referred to as BLSAs). Then, when a column selection line signal is activated, the data is transmitted to pairs of local input/output lines. Sequentially, the data is provided to data output buffers through corresponding global input/output lines and then output to the external of the semiconductor memory device.
In the DRAM 10, bit lines and local input/output lines which are not involved in the read operation are generally precharged to a voltage so as to increase a sensing speed and to prevent them from being floated. Pairs of local input/output lines are precharged to a voltage which corresponds to half of a source voltage or an operation voltage of a memory cell array. In other words, pairs of local input/output lines are precharged to a voltage equal to a precharge voltage for the bit lines. The operation voltage of the memory cell array generally is slightly less than or equal to the source voltage.
If a pair of local input/output lines are connected to local input/output line sense amplifiers, in order to increase the sensing speed of the local input/output line sense amplifiers, a technique for varying a precharge voltage for a pair of local input/output lines in accordance with an operation mode is applicable. For example, when a pair of local input/output lines are maximally amplified to have the operation voltage and a ground voltage, and are precharged to a first voltage, the precharging of the pair of local input/output lines may cause noise to change the level of the first voltage. In other words, the noise may influence a circuit which generates the first voltage, resulting in a drop in efficiency in sensing data from memory cells. In this case, the above-mentioned precharging technique may be applicable.
Until an active mode, for example, a read or write operation on memory cells starts, the pair of local input/output lines are precharged to the voltage equal to the precharge voltage for the bit lines. When a word line is enabled to enter an active mode, the pair of local input/output lines are precharged to a voltage equal to the operation voltage of the cell array. When the active mode is ended, the pair of local input/output lines are precharged to the voltage equal to the precharge voltage for the bit lines again.
A general precharging circuit to precharge a pair of local input/output lines in an active mode may not exhibit a satisfactory operation quality both under a short /RAS to /CAS delay time (hereinafter, referred to as a tRCD) condition and under a long tRCD condition. In other words, the precharging circuit may exhibit a satisfactory operation quality either under the short tRCD condition or the long tRCD condition. If the precharging circuit does not exhibit a satisfactory operation quality under the short tRCD condition, a bit line disturbance phenomenon may occur, and if the precharging circuit does not exhibit a satisfactory operation quality under the long tRCD condition, a low-voltage high-speed operation quality may be degraded.
For this reason, a technique for realizing a low-voltage high-speed operation while reducing or minimizing bit line disturbance is required to vary a precharging scheme in accordance with an operation mode to precharge local input/output lines in a read data path circuit of a DRAM which applies data read from memory cells to output buffers in a read operation.